As a semiconductor integrated circuit gets more miniaturized and comes to have a higher operating speed, the use of copper as a wiring material has been promoted, and the use of a low relative dielectric constant organic insulation film, a Si-based insulation film, or a porous insulation film as an interlayer insulation film provided between wirings has been promoted. However, it is difficult to chemically etch (dry-etch) copper. Specifically, a low vapor pressure of a Cu halide that is an etching product necessitates heating a wafer to high temperature, but a low heat-resistant material such as a mask suffers deterioration due to the high temperature of the wafer. Therefore, a damascene process is often adopted in processing a copper wiring. The damascene process is a method to form wirings by forming recessed portions (wiring trenches) in an interlayer insulation film, burying metal materials, which will become the wirings, in the recessed portions, and planarizing the surface by chemical mechanical polishing (CMP) or the like. The damascene process is categorized into a single damascene method and a dual damascene method. In the single damascene method, metal materials are separately buried in via portions (contact hole portions) and wiring portions, and are polished. In the dual damascene method, metal materials are simultaneously buried in via portions (contact hole portions) and wiring portions, and polished.
Here, a conventional single damascene method will be described. FIG. 16A and FIG. 16B to FIG. 20A and FIG. 20B are views showing, in the order of processes, a manufacturing method of a semiconductor device adopting the conventional single damascene method. FIG. 16A to FIG. 20A are plane views, and FIG. 16B to FIG. 20B are cross-sectional views taken along an I-I line in FIG. 16A to FIG. 20A respectively.
First, semiconductor elements (not shown) such as transistors are formed on a surface of a semiconductor substrate (not shown), and thereafter, as shown in FIG. 16A and FIG. 16B, a coating-type organic interlayer insulation film 101 and a CMP stopper film 102 are formed on or above the semiconductor elements in sequence. Then, wiring trenches are formed in the interlayer insulation film 101 and the CMP stopper film 102. Next, a barrier metal film 104 composed of TiN, TaN or the like is formed on the entire surface, and a copper film 105 is further formed on the entire surface so as to be buried in the wiring trenches. Next, the copper film 105 and the barrier metal film 104 are planarized by CMP or the like until the CMP stopper film 102 is exposed, whereby lower wirings 117 are formed. Thereafter, an etching stopper film 106 and an interlayer insulation film 107 are formed in sequence on the entire surface.
Subsequently, as shown in FIG. 17A and FIG. 17B, via holes (contact holes) 108 passing through the interlayer insulation film 107 and the etching stopper film 106 to reach the lower wirings 117 are formed. At this time, target positions where the via holes 108 are formed are positions right above the lower wirings 117, but due to deviation at the time of exposure or the like, they are often misaligned as shown in FIG. 17A and FIG. 17B.
Next, a barrier metal film 109 composed of TiN, TaN or the like is formed on the entire surface by a sputtering method or a CVD method, and a copper (Cu) film 110 as a conductor film is formed on the entire surface by a plating method or the like so as be buried in the via holes 108. Next, the Cu film 110 and the barrier metal film 109 on the interlayer insulation film 107 are removed by CMP, etch-back or the like, so that via plugs 118 composed of the barrier metal film 109 and the Cu film 110 are formed as shown in FIG. 18A and FIG. 18B.
Thereafter, as shown in FIG. 19A and FIG. 19B, an etching stopper film 111, a coating-type organic interlayer insulation film 112, and a CMP stopper film 113 are sequentially formed on the entire surface. Subsequently, a photoresist film (not shown) is formed on the CMP stopper film 113, and the photoresist film is patterned into a line pattern, so that a resist mask is formed. Then, using the resist mask, the CMP stopper film 113, the interlayer insulation film 112, and the etching stopper film 111 are etched, so that wiring trenches 114 are formed. At this time, target positions where the wiring trenches 114 are formed are positions right above the via plugs 118, but due to deviation at the time of exposure or the like, they are often misaligned as shown in FIG. 19A and FIG. 19B. Thereafter, the resist mask (photoresist film) is removed.
Next, a barrier metal film 115 composed of TiN, TaN or the like is formed on the entire surface, and a copper film 116 is formed on the entire surface so as to be buried in the wiring trenches 114. Next, the copper film 116 and the barrier metal film 115 are planarized by CMP or the like until the CMP stopper film 113 is exposed, so that upper wirings 119 are formed as shown in FIG. 20 and FIG. 20B.
In such a single damascene method, there occurs the misalignment between the lower wirings 117 and the via plugs 118 and between the via plugs 118 and the upper wirings 119, and these misalignments cause poor electrical connection. Further, the current exposure technology cannot completely prevent such misalignments. Moreover, this poor connection increases contact resistance (connection resistance) to increase a heat generation amount in these portions. As a result, long-term stability and reliability of the vias are lowered.
Further, this problem becomes more prominent in a structure where the width of the buried wirings is narrowed to the same level as the width of the via plugs due to the miniaturization and higher density of a semiconductor device, namely, in a structure where so-called borderless vias are formed.
Under such circumstances, disclosed is an art aiming at improving reliability of connection between wirings and via plugs (patent documents 1 and 2).
The patent document 1 (Japanese Patent Application Laid-open No. 2000-114259) describes a method in which recessions are formed around wirings and so on by using a microloading effect of etching. However, the microloading effect is a very unstable phenomenon, and thus it is extremely difficult to control an amount of the recessions formed by the phenomenon. Therefore, this method cannot be adopted in order to improve reliability of the electrical connection.
The patent document 2 (Japanese Patent Application Laid-open No. 2000-82738) describes a method in which via plugs reaching a surface of an interlayer insulation film, in which upper wirings are to be buried, and the via plugs and the upper wirings are made in contact with each other via side surfaces thereof. In this method, however, upper surfaces of the via plugs are exposed to plasma for a long time when the upper wirings are etched. Therefore, even though applicable to via plugs made of, for example, tungsten, this method is difficult to apply to via plugs made of copper. Further, an aspect ratio of each via hole becomes large, which causes a problem in terms of a burying property.
Moreover, the patent documents 1 and 2 aim only at improving reliability of the connection between upper wirings and via plugs, but when the borderless vias come to be adopted in accordance with the miniaturization of the semiconductor device, these prior arts are not sufficient and it is also necessary to ensure sufficient reliability of the electrical connection between via plugs and lower wirings.
Patent Document 1
Japanese Patent Application Laid-open No. 2000-114259
Patent Document 2
Japanese Patent Application Laid-open No. 2000-82738